For processing a semiconductor wafer or a display glass to a semiconductor chip or a display element, a designed electric circuit should be built on the semiconductor wafer or the display glass by using a photolithography process. As the circuit integration increases, high-resolution patterning is further required in the photolithography process. One of methods for obtaining the high-resolution pattern uses a light with short wavelength as an exposure source, main parameter for defining the resolution, and another method is to fill liquid having a refractive index larger than that of air between a photo sensitizer and a lens so as to make a numeral aperture (NA) over 1. Still another method is to make k1, one of process parameters, less than 0.3 by introducing an additional process. In detail, KrF laser light whose wavelength is 248 nanometers is used as an exposure source to manufacture a 90-to-200-nanometer-device, and ArF laser light whose wavelength is 193 nanometers is used as an exposure source to produce a semiconductor chip with 60-to-90-nanometer-pattern resolution. In order to obtain a device having 40-to-60-nanometer-ultra fine pattern resolution, during the exposure, is used an immersion lithography process which makes the numeral aperture (NA) more than 1 by filing deionized (DI) water having 1.34 of a refractive index between a photoresist layer coated on a wafer and a projection lens, instead of air with 1 of a refractive index.
The technique under the study for manufacturing 30-nanometer device is a double patterning process which is a modification of a conventional single photolithography process. The double patterning process reduces a process parameter k1 0.25 and less by twice repeating the conventional single photolithography process, to form ultra-fine patterns. As another methods for reducing the process parameter k1, there are a double expose patterning process (See: FIG. 1) and a spacer patterning technology (SPT) (see: FIG. 2). In the double expose patterning process, an exposure process is carried out twice to obtain a pattern with a desired resolution. In SPT, on a sacrifice pattern is formed a spacer by CVD (Chemical Vapor Deposition) after an initial exposure process, and then the sacrifice pattern is removed to obtain a pattern with a desired resolution.
However, the double expose patterning process has a problem that an overlay accuracy at the second exposure cannot be secured. In SPT employing an inorganic sacrifice layer, a CVD process and an etching process are further required so the SPT is more complicated and production cost highly increases. Also, in SPT employing an organic sacrifice layer, the thickness of sacrifice layer cannot be enough obtained.
In order to overcome those problems, the present invention discloses a self-consistent interlayer lithography process in which is employed a mirror interlayer having a larger refractive index than that of a second photoresist pattern and serving as a protecting layer of a first photoresist pattern during the formation of the second photoresist pattern. Also, the present invention discloses a composition of the mirror interlayer and a photoresist composition having a regulated sensitivity, which are used for the self-consistent interlayer lithography process.